1) Field of the Invention
The present invention relates to a data decision circuit which compares phases of an input data signal and a determined data signal, and determines a phase relationship between the input data signal and the clock signal in order to determine data values carried by the input data signal. The present invention also relates to an optical receiver apparatus which receives an optical signal and determines data values carried by the optical signal.
2) Description of the Related Art
Recently, areas in which broadband transmission of information (such as moving images) is used are rapidly expanding. For example, technologies for transmitting high-speed signals have been introduced into subscriber systems and systems inside switching centers, as well as trunk line systems. Under such circumstances, demands for a digital transmission system which enables low-cost, large-capacity signal transmission are increasing.
In receivers used in digital transmission systems, it is essential to accurately discriminate “0” and “1” bits and determine (recover) data values carried by transmitted data signals. In order to achieve the accurate determination and recovery of data values, data decision circuits are used. The data decision circuits compare phases of an input data signal and a determined data signal representing determined data values, and control a phase of a decision clock so as to realize an appropriate phase relationship between the phases of the input data signal and the clock signal.
The conventional data decision circuits detect only rising or only falling of the input data signal, and controls phases of transition points of a clock signal which is used in data decision, so as to maintain a predetermined phase difference between the transition points of the clock signal and the detected rising or falling of the input data signal, for example, as disclosed in Japanese unexamined patent publication (Kokai) No. 2000-68991.
However, in the conventional data decision circuits as above, when a pulse width (or a duty ratio) of an input data signal varies, it is difficult to accurately determine data values carried by the input data signal, and therefore reliability of data decision decreases.
The above problem in the conventional data decision circuits is explained in detail with reference to FIGS. 13(A) to 13(C) for the case where a conventional data decision circuit detects rising of an input data signal, and controls phases of transition points of a clock signal. That is, it is assumed that this data decision circuit detects rising of the input data signal, and controls transition points of the clock signal for use in data decision so as to maintain a predetermined phase (time) difference P between each rising of the input data signal and a transition (rising) of the clock signal which occurs subsequently to the rising of the input data signal. Usually, the predetermined phase (time) difference P is equal to one-half of a timeslot of the input data signal or the duration of the “1” state in one bit of the input data signal, as illustrated in FIG. 13(A).
If the duty ratio of the input data signal does not vary, the conventional data decision circuit operates without the above problem. However, in actual operations of data decision circuits, waveshapes of transmitted and received signals vary due to variations in temperature and power supply, and therefore duty ratios of input data signals also vary.
When the duty ratio of the input data signal greatly decreases (i.e., the duration of the “1” state decreases), for example, as illustrated in FIG. 13(B), the time from the rising of the clock signal to the subsequent falling of the input data signal (i.e., a phase margin for holding the data value “1”) also decreases since the phase (time) difference P between the rising of the input data signal and a rising of the clock signal occurring subsequently to the rising of the input data signal is controlled to be constant. Therefore, the input data signal is likely to be incorrectly recovered (determined).
Further, when the duty ratio of the input data signal increases (i.e., the duration of the “1” state increases), for example, as illustrated in FIG. 13(C), the above problem of the decrease in the phase margin for the data holding operation does not arise. However, the time from the falling of the input data signal to the next transition (rising) of the clock signal (i.e., a phase margin for setting up a data holding circuit) decreases. Therefore, the operation of the data decision circuit for determining a data bit “0” following a data bit “1” is likely to become unstable.
As described above, in the operations of the conventional data decision circuits, the operation becomes unstable when the duty ratio of the input data signal varies, since the phase (time) difference P between each rising (or each falling) of the input data signal and a rising or falling of the clock signal is controlled to be constant.